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Digital Logic Design - CS302 - VU Video Lectures

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Digital Representing Of Quantities, Digital Systems And Digital Values, Binary Number System, Advantages Of Working In The Digital Domain, Information Processing By A Digital System, Digital Components And Their Internal Working, Combinational Logic Circuits And Functional Devices, Sequential Logic And Implementation, Programmable Logic Devices (Plds), Memory, Analogue To Digital And Digital To Analogue Conversion And Interfacing, Number Systems And Codes.
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Binary To Decimal Conversion, Decimal To Binary Conversion, Converting Decimal Fractions To Binary, Repeated Multiplication-By-2 Method, Binary Arithmetic, Signed And Unsigned Binary Numbers, 1’s & 2’s Complement, Addition And Subtraction Operations With Signed Binary, Range Of Signed And Unsigned Binary Numbers.
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Range Of Numbers And Overflow, Determining Overflow Conditions For 2’s Complement Numbers, Floating-Point Numbers, Decimal Number Floating-Point Format, Representing Negative Exponent Values, Representing Zero And Infinity Values, Representing A Decimal Fraction Number In 32-Bit Single-Precision Floating Point Format, Arithmetic Operations On Floating Point Numbers, Hexadecimal Numbers, Counting In Hexadecimal, Binary To Hexadecimal Conversion, Hexadecimal To Binary Conversion, Hexadecimal Addition And Subtraction.
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Number Systems & Codes, Octal Numbers, Counting In Octal Number System, Binary To Octal Conversion, Octal To Binary Conversion, Decimal To Octal Conversion, Octal To Decimal Conversion, Octal Addition And Subtraction, Working With Different Binary Representations, Alternate Forms Of Binary Representations, The Excess Code, The BCD Code, BCD Addition, The Gray Code, Gray Code Application, Alphanumeric Codes, ASCII Code, Parity Method, Even Parity Method.
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LOGIC GATES, AND Gate, OR Gate, NOT Gate, AND & OR Gate Alternate Symbols, NAND Gate, NAND Gate As A Universal Gate, NOR Gate.
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Logic Gates & Operational Characteristics, NOR Gate As A Universal Gate, NOT Gate Implementation, OR Gate Implementation, AND Gate Implementation, NAND-NOR Universal Gates, NAND And NOR Gate Applications, Exclusive-OR And Exclusive-NOR Gates, XOR And XNOR Gate Applications, Digital Circuits And Operational Characteristics, TTL/CMOS NOT Gate Operation, Integrated Circuit Technologies, Types Of IC Logic Gates, Performance Characteristics And Parameters.
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Digital Circuits And Operational Characteristics, DC Supply Voltage, Logic Levels And Noise Margin, Effect Of Noise On The Operation Of A CMOS AND Gate, Effect Of Noise On The Operation Of A CMOS AND Gate Circuit, Noise Margin, Propagation Delay, Speed-Power Product (SPP), Fan-Out And Loading.
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Boolean Algebra And Logic Simplification, Boolean Algebra Definitions, Boolean Addition, Boolean Multiplication, Laws Of Boolean Algebra, Demorgan’s Theorems, Boolean Analysis Of Logic Circuits, Simplification Using Boolean Algebra, Standard Form Of Boolean Expressions, Implementation Of An SOP And POS Expression.
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Boolean Algebra And Logic Simplification, Finding The Boolean Expression, Putting The Results In Truth Table Format, Simplification Of Boolean Expression, Putting The Result In Truth Table Format, Implementing Logic Circuit From Simplified Boolean Expression, Standard SOP Form, Standard POS Form, Minterms And Maxterms, Binary Representation Of A Standard Product Term Or Minterm, Binary Representation Of A Standard Sum Term Or Maxterm, Converting Standard SOP Into Standard POS, Verifying POS Expression Is Equivalent To SOP Expression, Boolean Expressions And Truth Tables, Converting POS Expression To Truth Table Format.
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Karnaugh Map & Boolean Expression Simplification, The 3-Variable Karnaugh Map, The 4-Variable Karnaugh Map, Grouping And Adjacent Cells, Mapping A Standard SOP Expression, Mapping A Non-Standard SOP Expression, Simplification Of SOP Expressions Using The Karnaugh Map, Mapping Directly From Function Table, Don’t Care Conditions.
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Karnaugh Map & Boolean Expression Simplification, Mapping A Standard POS Expression, Karnaugh Map Simplification Of POS Expressions, Converting Between POS And SOP Using The K-Map, Five-Variable Karnaugh Map, Simplification Of 5-Variable Karnaugh Map, Functions Having Multiple Outputs.
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Comparator, Quine-Mccluskey Simplification Method, Comparator Circuit, Odd-Prime Number Detector.
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Odd-Prime Number Detector, Combinational Circuit Implementation Based On SOP Form, Combinational Circuit Implementation Based On POS Form, Design And Implementation Of Combinational Circuits, Design And Implementation Of Combinational Circuits, POS Based Implementation Of The Adjacent 1s Detector Circuit, Operation Of Adjacent 1s Detector Circuit, Active Low/High Inputs And Outputs, Implementation Of An Odd-Parity Generator Circuit.
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Implementation Of An Odd-Parity Generator Circuit, Operation Of Odd-Parity Generator Circuit, XOR And XNOR Gates, Combinational Function Devices, Half Adder And Full Adder, Half-Adder Function Table, Half-Adder Sum & Carry Out Boolean Expressions, Half-Adder Logic Circuit, Full-Adder Sum & Carry Out Boolean Expressions, Carry Propagation, Look-Ahead Carry Circuits, Carry Outputs In Terms Of Carry Propagate And Carry Generate, MSI Adders.
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Bcd Adder, Connection Of Invalid Bcd Detector Circuit To Second Adder, 2-Digit Bcd Adder, Subtraction, A 4-Bit Adder/Subtracter Unit, An 8-Bit Adder/Subtracter Unit, Arithmetic And Logic Unit (Alu), Implementing 16-Bit Alu, Group-Carry Look-Ahead.
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16-BIT ALU, Iterative Circuit Based Comparator, MSI 4-Bit Comparator, Decoders, Basic Decoder, Applications Of Decoders, MSI Decoder.
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THE 74XX138 3-TO-8 DECODER, Implementing Standard SOP And POS Boolean Expressions, BCD To 7-Segment Decoder, MSI Seven-Segment Decoder, BCD-To-Decimal Decoder, Encoder, Binary Encoder, Priority Encoders, Cascading Priority Encoders, Decimal-To-BCD Encoder, Multiplexer.
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Expanding Multiplexers, Applications Of Multiplexers.
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Demultiplexer, Applications Of Demultiplexer, Programmable Logic Devices, Programmable Arrays Of AND Gates And OR Gates, PAL Circuit And Programming, PAL Outputs.
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Implementing Constant 0s And 1s, Implementing Odd-Prime Number Function, GAL Operation, Programming Of Plds, The GAL22V10, OLMC Combinational Mode, Tri-State Buffers, The GAL22V10 Array, The GAL16V8. Simple Mode, Complex Mode,. Test Vectors, The ABEL Input File.
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The GAL16V8, OLMC For GAL16V8, Tri-State Buffer And OLMC Output Pin, The Feedback From The OLMC To The AND Gate Array Input, The Output Of The Sum Of Product Term, Simple Mode, Complex Mode, Introduction To ABEL, Boolean Operations And Boolean Notations.
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ABEL Input File Of A QUAD 1-OF-4 MUX, Implementation Of Quad MUX, Sequential Circuits, Latches And Flip-Flops, The NAND Gate Based S-R (Set-Reset) Latch, The NOR Gate Based S-R (Set-Reset) Latch.
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Application Of S-R LATCH, The Gated S-R Latch, The Gated D Latch, Application Of Gated D Latch, Edge-Triggered Flip-Flop, Edge-Triggered S-R Flip-Flop, Edge-Triggered D Flip-Flop, Edge-Triggered J-K Flip-Flop, Asynchronous Preset And Clear Inputs, The 74HC74 Dual Positive-Edge Triggered D Flip-Flop, The 74HC112 Dual Positive-Edge Triggered J-K Flip-Flop, Master-Slave Flip-Flops, Flip-Flop Operating Characteristics, Propagation Delay, Set-Up Time, Hold Time, Maximum Clock Frequency, Pulse Width, Power Dissipation.
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Applications Of Edge-Triggered D Flip-Flop, Data Storage Using D-Flip-Flop, Synchronizing Asynchronous Inputs Using D Flip-Flop, Parallel Data Transfer Using D Flip-Flop, Edge-Triggered J-K Flip-Flop, Applications Of Edge-Triggered J-K Flip-Flop.
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Asynchronous Preset And Clear Inputs, The 74HC74 Dual Positive-Edge triggered D flip-flop, The 74HC112 Dual Positive-Edge triggered J-K flip-flop, Master-Slave Flip-Flops, Flip-Flop Operating Characteristics, Maximum Clock Frequency, Pulse Width, Power Dissipation, One-Shot Mono-stable multi-vibrator.
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THE 555 TIMER, Timing Problem in flip-flop circuits, Clock Skew, Race Conditions, Counters, Asynchronous Counters (Ripple Counters), Propagation Delay, Mod-n Counters, Mod-10 Counter (Decade Counter), Integrated Circuit Asynchronous Counters.
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Down Counters, Down Counter With Truncated Sequence, Synchronous Counters, 3-Bit & 4-Bit Synchronous Counters, 4-Bit Synchronous Decade Counter.
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Timing Diagram Of A Synchronous Decade Counter, Mod-n Synchronous Counter, Integrated Circuit Synchronous Counters, Cascading Counters, Integrated Circuit Counters with Truncated Sequences, Cascaded Counters with Truncated Sequences, Up-Down Counter.
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Integrated Circuit Up/Down Decade Counter, Counter Decoding, Counter Applications, Design Of Synchronous Counters, Sequential Circuit (State Machine), Design Procedure, Implementing A 3-Bit Up/Down Counter.
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Digital Clock, Design Of Synchronous Counters, Clocked Synchronous State Machines.
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Next-State Table, Flip-Flop Transition Table, Karnaugh Maps, Logic Expressions For Flip-Flop Inputs, Sequential Circuit Implementation, S-R Flip-Flop Based Implementation, Flip-Flop Transition Table, Karnaugh Maps, Sequential Circuit Implementation.
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D Flip-Flop Based Implementation, Flip-Flop Transition Table, Karnaugh Maps, Logic expressions for Flip-flop Inputs, Sequential Circuit Implementation, State Reduction.
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STATE ASSIGNMENT, Moore Machine, Karnaugh Maps, Implementation, Mealy Machine.
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Shift Registers, Serial In/Shift Right/Serial Out Operation, Serial In/Shift Left/Serial Out Operation, Serial In/Parallel Out Operation, Parallel In/Serial Out Operation, Parallel In/Parallel Out Operation, Rotate Right Operation, Rotate Left Operation, Shift Register Counters.
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Applications Of Shift Registers, Serial-To-Parallel Converter, Keyboard Encoder, Programmable Sequential Logic, The Registered Mode, Software Mode Specification, Example1: Parallel Input/Parallel Output 8-Bit Register With Inverted Outputs.
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Bit Up/Down Counter, Using A Truth-Table To Specify Sequential Circuit, Using A State Diagram To Specify Sequential Circuit, Elevator Control System, Input And Output Signals, Elevator State Diagram, Input Latches.
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Reduced Number Of Input Latches, The ABEL Input File For Elevator State Machine, Traffic Signal Control System, Traffic Signal Controller Inputs And Outputs.
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Switching Of Traffic Lights, Analysis Of Clocked Synchronous State Machines, State Machine Analysis.
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Memory Organization, Memory Capacity And Density, Memory Signals And Basic Operations On Memory, Read And Write Signals, Address Signals, Data Signals, Memory Select Or Enable Signal, Memory Read Operation, Memory Write Operation, Memory Types, Random Access Memory (RAM).
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Decoding Large Memories, Memory Read Cycle, Memory Write Cycle, Synchronous Burst Sram, Dynamic Ram, Address Multiplexing.
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Read And Write Cycles, Burst Refresh And Distributed Refresh, RAS Only Refresh And CAS Before RAS Refresh, Types Of Drams, ROM Read-Only Memory, Mask ROM, ROM Applications, EPROM Erasable PROM, Programming EPROM, EEPROM Electrically Erasable PROM, FLASH Memory, FLASH Memory Operations, Programming Operation, Read Operation, Erase Operation.
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Flash Memory Array, Memory Summary, Special Type Of Memories, Implementing FIFO Memory Using RAM.
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Last In-First Out (Lifo) Memory, Memory Expansion, Memory Map, Expanding Data Unit Size, Expanding Memory Locations, Expanding Data Unit Size and Memory Locations, Address Decoders, Introduction to FPGAs.
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The Logic Block, The Logic Element, The Look-Up Table, Analogue to Digital Conversion, Sample and Hold Operation, Operational Amplifier (Op-Amp), Flash Analogue-to Digital Converter, Dual-Slope Analogue to Digital Converter.
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Analogue-to-Digital Converter Errors, Digital to Analogue Conversion, Binary-Weighted-Input Digital to Analogue Converter, The R/2R Ladder Digital to Analogue Converter, Performance characteristics of Digital-to-Analogue Converters.